The present invention relates to a semiconductor device and a manufacturing method thereof which can be used appropriately for, e.g., a semiconductor device including a solid-state image sensing element and a manufacturing method thereof.
As a solid-state image sensing element (hereinafter referred to simply as an image sensing element) used in a digital camera or the like, a CMOS (Complementary Metal Oxide Semiconductor) image sensor using a CMOS has been intensively developed. The CMOS image sensor has a plurality of pixels which are arranged in a matrix pattern and each of which detects light. In each of the plurality of pixels, a photoelectric conversion element such as a photodiode which detects light and generates charges is formed. A photodiode PD is a pn-junction diode and includes, e.g., a plurality of n-type or p-type impurity regions, i.e., semiconductor regions.
U.S. Pat. No. 5,965,875 (Patent Document 1) discloses a technique in which, in an active pixel cell imaging array, an N-type region is formed over a P-type silicon substrate, a P-type region is formed over the N-type region, and an N-type region is further formed over the P-type region. Japanese Unexamined Patent Publication No. 2007-180539 (Patent Document 2) discloses a technique in which a CMOS image sensor includes a blue photodiode region and a red photodiode region having a given gap between itself and the blue photodiode region and formed deeper than the blue photodiode region. Japanese Unexamined Patent Publication No. 2008-300835 (Patent Document 3) discloses a technique in which, in a vertical CMOS image sensor, a plurality of photodiodes are vertically formed to a predetermined depth in a substrate.
Japanese Unexamined Patent Publication No. 2008-91840 (Patent Document 4) discloses a technique in which, in a solid-state image sensing device in which a plurality of pixels each having a photodiode and a transistor which reads the charges obtained by the photodiode are arranged to form an image sensing region, an independent first-conductivity-type region separated from the photodiode and the transistor is provided. Japanese Translation of PCT Application No. 2009-510777 (Patent Document 5) discloses a technique in which an image sensor has a first-conductivity-type first layer extending over an entire image region and a second-conductivity-type second layer, the first layer is present between a substrate and the second layer, and a plurality of photodetectors are disposed in the second layer so as to be adjacent to the first layer. Japanese Unexamined Patent Publication No. 2008-300826 (Patent Document 6) discloses a technique in which a multi-well CMOS image sensor has a plurality of photodiodes formed vertically in a predetermined region of a substrate.